1. Field of the Invention
The present invention relates to a technique for evaluating a form of a diffusion layer region formed in a semiconductor substrate.
2. Description of the Background Art
Evaluating two-dimensional or three-dimension structure of a diffusion layer, which is one of elements constituting a device and on which characteristics of a transistor is highly dependent, is of great importance. For example, a technique for evaluating a form of a diffusion layer region is shown in "Semiconductor Evaluation Technique" (Edited by Takashi Katoda, Sangyo Tosho Publishing Company, 1989, pp. 136 to 137). Specifically, a cleaved sample of semiconductor device is pretreated with Sirtl etchant to manifest a diffusion layer, and then the manifested diffusion layer is evaluated using Scanning Electron Microscopy (SEM). The etch rate of Sirtl etchant to silicon is dependent on an impurity concentration in the silicon, and specifically the silicon is more easily etched as its impurity concentration becomes higher. This method takes advantage of this property of silicon and makes it possible to manifest a diffusion layer region having an impurity concentration of 10.sup.19 atms/cm.sup.3 level or more.
In cutting-edge devices, however, with an increase of cases where a diffusion layer region of low impurity concentration is formed in a semiconductor substrate for field relieving, there arises a problem that evaluation of a form of a diffusion layer region of low impurity concentration is not achieved with high accuracy since the diffusion layer region of low impurity concentration can not be manifested by the above pretreatment with the Sirtl etchant.
Further, a silicon oxide film serving as an interlayer insulation film is needlessly etched by the pretreatment with the Sirtl etchant, and accordingly, it becomes difficult to perform a structural evaluation of the whole device with good reproducibility.